Referenceless clock chips are able to generate a clock without the benefit of a direct external reference clock input, e.g., without a crystal oscillator source. Thus, the chip does not require routing for a reference clock input and does not consume pins on the chip for the reference clock. However, the referenceless clock is not tightly controlled, having a frequency variation up to thirty percent or more from chip to chip. This variation arises from process, voltage, and temperature (PVT) differences in manufacturing processes and in operating conditions, both from die to die and from wafer to wafer. Resultantly, while the free running oscillator of a referenceless clock can have a target frequency, e.g., 120 MHz, the actual operating frequency of a given die can vary +/−50% from the target frequency, e.g., 60 MHz to 180 MHz. This variation is amenable to a chip design without critical timing functions, e.g., setup and hold times, etc. For example, simple devices such as a flip-flop or a state machine can usually withstand the wide frequency ranges of a referenceless clock, assuming the timing requirements of the circuit are suitable for the noted frequency range. Another drawback to a referenceless clock chip is that overall time to startup time can change, e.g., being fast for a chip having a high frequency referenceless clock and being slow for a chip with a low frequency referenceless clock.
In a network setting, IEEE standards dictate different protocols for chip initialization and bring up, e.g., depending on whether they are long reach (“LR”) or short reach (“SR”). There are two categories for bringing up devices. The first category is a physical medium attachment (“PMA”) interface, typically for short-reach (SR) devices, which simply starts communicating without any negotiating. These devices communicate over lower loss medium, with typical losses of less than 15 dB at Nyquist. The PMA interface also performs functions such as clock recovery, data recovery, and clock generation. The second category is a physical medium dependent (“PMD”) interface, typically for long-reach (LR) devices that communicates with a backplane. These devices communicate over higher loss medium, with typical losses of greater than 25 dB at Nyquist. Example specifications included IEEE 802.3bj 100GBASE-CR4, 100GBASE-KR, etc. For PMD interfaces, executing an autonegotiation (“AN”) protocol is required to establish an agreed operating frequency and lane use between the two devices, e.g., between a host network processor and the optical module, before the devices can start transmitting (mission mode) data between them. Autonegotiation requires a pulse width of 3.2 ns+/−100 parts per million (“ppm”). This stringent clock spec cannot be satisfied solely with a referenceless clock. Thus, a typical device with PMD connectivity uses a direct input from a reference clock in order to perform the autonegotiation with a device on the backplane.